Opcode/Instruction | Op/En | 64/32bit Mode | CPUID Feature Flag | Description |

VEX.DDS.LIG.128.66.0F38.W1 9F /r VFNMSUB132SD xmm0, xmm1, xmm2/m64 |
A | V/V | FMA | Multiply scalar double-precision floating-point value from xmm0 and xmm2/mem, negate the multiplication result and subtract xmm1 and put result in xmm0. |

VEX.DDS.LIG.128.66.0F38.W1 AF /r VFNMSUB213SD xmm0, xmm1, xmm2/m64 |
A | V/V | FMA | Multiply scalar double-precision floating-point value from xmm0 and xmm1, negate the multiplication result and subtract xmm2/mem and put result in xmm0. |

VEX.DDS.LIG.128.66.0F38.W1 BF /r VFNMSUB231SD xmm0, xmm1, xmm2/m64 |
A | V/V | FMA | Multiply scalar double-precision floating-point value from xmm1 and xmm2/mem, negate the multiplication result and subtract xmm0 and put result in xmm0. |

Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |

A | ModRM:reg (r, w) | VEX.vvvv (r) | ModRM:r/m (r) | NA |

VFNMSUB132SD: Multiplies the low packed double-precision floating-point value from the first source operand to the low packed double-precision floating-point value in the third source operand. From negated infinite precision intermediate result, subtracts the low double-precision floating-point value in the second source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand). VFNMSUB213SD: Multiplies the low packed double-precision floating-point value from the second source operand to the low packed double-precision floating-point value in the first source operand. From negated infinite precision intermediate result, subtracts the low double-precision floating-point value in the third source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand). VFNMSUB231SD: Multiplies the low packed double-precision floating-point value from the second source to the low packed double-precision floating-point value in the third source operand. From negated infinite precision intermediate result, subtracts the low double-precision floating-point value in the first source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand). VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 64-bit memory location and encoded in rm_field. The upper bits ([VLMAX-1:128]) of the YMM destination register are zeroed. Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column. See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior” in the *Intel® 64 and* *IA-32 Architectures Software Developer’s Manual, Volume 1.*

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations with infinite precision inputs and outputs (no rounding). VFNMSUB132SD DEST, SRC2, SRC3 DEST[63:0] ← RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) - SRC2[63:0]) DEST[127:64] ← DEST[127:64] DEST[VLMAX-1:128] ← 0 VFNMSUB213SD DEST, SRC2, SRC3 DEST[63:0] ← RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) - SRC3[63:0]) DEST[127:64] ← DEST[127:64] DEST[VLMAX-1:128] ← 0 VFNMSUB231SD DEST, SRC2, SRC3 DEST[63:0] ← RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) - DEST[63:0]) DEST[127:64] ← DEST[127:64] DEST[VLMAX-1:128] ← 0

VFNMSUB132SD: __m128d _mm_fnmsub_sd (__m128d a, __m128d b, __m128d c);

VFNMSUB213SD: __m128d _mm_fnmsub_sd (__m128d a, __m128d b, __m128d c);

VFNMSUB231SD: __m128d _mm_fnmsub_sd (__m128d a, __m128d b, __m128d c);

Overflow, Underflow, Invalid, Precision, Denormal

See Exceptions Type 3