|Opcode/Instruction||Op/En||64/32-bit Mode||CPUID Feature Flag||Description|
|66 0F 50 /r MOVMSKPD reg, xmm||RM||V/V||SSE2||Extract 2-bit sign mask from xmm and store in reg. The upper bits of r32 or r64 are filled with zeros.|
|VEX.128.66.0F.WIG 50 /r VMOVMSKPD reg, xmm2||RM||V/V||AVX||Extract 2-bit sign mask from xmm2 and store in reg. The upper bits of r32 or r64 are zeroed.|
|VEX.256.66.0F.WIG 50 /r VMOVMSKPD reg, ymm2||RM||V/V||AVX||Extract 4-bit sign mask from ymm2 and store in reg. The upper bits of r32 or r64 are zeroed.|
|Op/En||Operand 1||Operand 2||Operand 3||Operand 4|
|RM||ModRM:reg (w)||ModRM:r/m (r)||NA||NA|
Extracts the sign bits from the packed double-precision floating-point values in the source operand (second operand), formats them into a 2-bit mask, and stores the mask in the destination operand (first operand). The source operand is an XMM register, and the destination operand is a general-purpose register. The mask is stored in the 2 low-order bits of the destination operand. Zero-extend the upper bits of the destination.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. The default operand size is 64-bit in 64-bit mode. 128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register. VEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose register. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
(V)MOVMSKPD (128-bit versions) DEST ← SRC DEST ← SRC IF DEST = r32 THEN DEST[31:2] ← 0; ELSE DEST[63:2] ← 0; FI VMOVMSKPD (VEX.256 encoded version) DEST ← SRC DEST ← SRC DEST ← SRC DEST ← SRC IF DEST = r32 THEN DEST[31:4] ← 0; ELSE DEST[63:4] ← 0; FI
|MOVMSKPD:||int _mm_movemask_pd ( __m128d a)|
See Exceptions Type 7; additionally
|#UD||If VEX.vvvv != 1111B.|