| Opcode/Instruction | Op/En | 64-Bit Mode | Compat/Leg Mode | Description |
| 0F 2D /r CVTPS2PI mm, xmm/m64 | RM | Valid | Valid | Convert two packed single-precision floatingpoint values from xmm/m64 to two packed signed doubleword integers in mm. |
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| RM | ModRM:reg (w) | ModRM:r/m (r) | NA | NA |
Converts two packed single-precision floating-point values in the source operand (second operand) to two packed signed doubleword integers in the destination operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX technology register. When the source operand is an XMM register, the two single-precision floating-point values are contained in the low quadword of the register. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.
CVTPS2PI causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floatingpoint exception is pending, the exception is handled before the CVTPS2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]); DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);
| CVTPS2PI: | __m64 _mm_cvtps_pi32(__m128 a) |
Invalid, Precision.
See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.