CPUID—CPU Identification

Instruction Operand Encoding

Description

The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction operates the same in non-64-bit modes and 64-bit mode. CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers.¹ The instruction’s output is dependent on the contents of the EAX register upon execution (in some cases, ECX as well). For example, the following pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return Value and the Vendor Identification String in the appropriate registers:

MOV EAX, 00H CPUID

Table 3-17 shows information returned, depending on the initial value loaded into the EAX register. Table 3-18 shows the maximum CPUID input value recognized for each family of IA-32 processors on which CPUID is implemented.

Two types of information are returned: basic and extended function information. If a value entered for CPUID.EAX is higher than the maximum input value for basic or extended function for that processor then the data for the highest basic information leaf is returned. For example, using the Intel Core i7 processor, the following is true: CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *) CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *) CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *) CPUID.EAX = 0CH (* INVALID: Returns the same information as CPUID.EAX = 0BH. *) CPUID.EAX = 80000008H (* Returns linear/physical address size data. *) CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0BH. *)

If a value entered for CPUID.EAX is less than or equal to the maximum input value and the leaf is not supported on that processor then 0 is returned in all the registers. For example, using the Intel Core i7 processor, the following is true: CPUID.EAX = 07H (*Returns EAX=EBX=ECX=EDX=0. *)

When CPUID returns the highest basic leaf information as a result of an invalid input EAX value, any dependence on input ECX value in the basic leaf is honored.

CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed.

See also:

“Serializing Instructions” in Chapter 8, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

“Caching Translation Information” in Chapter 4, “Paging,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Table 3-17. Information Returned by CPUID Instruction

Initial EAX

Notes: * The nearest power-of-2 integer that is not smaller than EBX[23:16] is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package. This field is only valid if CPUID.1.EDX.HTT[bit 28]= 1.

Notes: Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use the PSN flag (returned using CPUID) to check for PSN support before accessing the feature.

See AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618) for more information on PSN.

CPUID leaves > 3 < 80000000 are visible only when IA32_MISC_ENABLE.BOOT_NT4[bit 22] = 0 (default).

Deterministic Cache Parameters Leaf

Notes: * If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0. Invalid sub-leaves of EAX = 04H: ECX = n, n > 3. ** Add one to the return value to get the result. ***The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) is the number of unique initial APIC IDs reserved for addressing different logical processors sharing this cache **** The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of bits of the initial APIC ID. ***** The returned value is constant for valid initial values in ECX. Valid ECX values start from 0.

MONITOR/MWAIT Leaf

NOTE:

NOTE:

* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Invalid sub-leaves of EAX = 07H: ECX = n, n > 0.

Direct Cache Access Information Leaf

Notes: * Software should use this field (EAX[4:0]) to enumerate processor topology of the system.

** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software and platform hardware configurations.

*** The value of the “level type” field is not related to level numbers in any way, higher “level type” values do not mean higher levels. Level type field has the following encoding: 0 : invalid 1 : SMT 2 : Core 3-255 : Reserved

Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)

Notes: * L2 associativity field encodings: 00H - Disabled 01H - Direct mapped 02H - 2-way 04H - 4-way 06H - 8-way 08H - 16-way 0FH - Fully associative

Notes:

INPUT EAX = 0: Returns CPUID’s Highest Value for Basic Processor Information and the Vendor Identification String

When CPUID executes with EAX set to 0, the processor returns the highest value the CPUID recognizes for returning basic processor information. The value is returned in the EAX register (see Table 3-18) and is processor specific. A vendor identification string is also returned in EBX, EDX, and ECX. For Intel processors, the string is “GenuineIntel” and is expressed: EBX ← 756e6547h (* "Genu", with G in the low eight bits of BL *) EDX ← 49656e69h (* "ineI", with i in the low eight bits of DL *) ECX ← 6c65746eh (* "ntel", with n in the low eight bits of CL *)

INPUT EAX = 80000000H: Returns CPUID’s Highest Value for Extended Processor Information

When CPUID executes with EAX set to 80000000H, the processor returns the highest value the processor recognizes for returning extended processor information. The value is returned in the EAX register (see Table 3-18) and is processor specific.

Table 3-18. Highest CPUID Source Operand for Intel 64 and IA-32 Processors

Highest Value in EAX Intel 64 or IA-32 Processors

IA32_BIOS_SIGN_ID Returns Microcode Update Signature

For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 9 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

INPUT EAX = 1: Returns Model, Family, Stepping Information

When CPUID executes with EAX set to 1, version information is returned in EAX (see Figure 3-5). For example: model, family, and processor type for the Intel Xeon processor 5100 series is as follows:

• Model — 1111B
• Family — 0101B
• Processor Type — 00B

See Table 3-19 for available processor type values. Stepping IDs are provided as needed.

Extended Family ID (0) Extended Model ID (0) Processor Type Family (0FH for the Pentium 4 Processor Family) Model

Reserved

OM16525

NOTE See Chapter 17 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for information on identifying earlier IA-32 processors.

The Extended Family ID needs to be examined only when the Family ID is 0FH. Integrate the fields into a display using the following rule:

IF Family_ID ≠ 0FH THEN DisplayFamily = Family_ID; ELSE DisplayFamily = Extended_Family_ID + Family_ID; (* Right justify and zero-extend 4-bit field. *) FI; (* Show DisplayFamily as HEX field. *)

The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. Integrate the field into a display using the following rule:

IF (Family_ID = 06H or Family_ID = 0FH) THEN DisplayModel = (Extended_Model_ID « 4) + Model_ID; (* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*) ELSE DisplayModel = Model_ID; FI; (* Show DisplayModel as HEX field. *)

INPUT EAX = 1: Returns Additional Information in EBX

When CPUID executes with EAX set to 1, additional information is returned to the EBX register:

• Brand index (low byte of EBX) — this number provides an entry into a brand string table that contains brand strings for IA-32 processors. More information about this field is provided later in this section.
• CLFLUSH instruction cache line size (second byte of EBX) — this number indicates the size of the cache line flushed with CLFLUSH instruction in 8-byte increments. This field was introduced in the Pentium 4 processor.
• Local APIC ID (high byte of EBX) — this number is the 8-bit ID that is assigned to the local APIC on the processor during power up. This field was introduced in the Pentium 4 processor.

INPUT EAX = 1: Returns Feature Information in ECX and EDX

When CPUID executes with EAX set to 1, feature information is returned in ECX and EDX.

• Figure 3-6 and Table 3-20 show encodings for ECX.
• Figure 3-7 and Table 3-21 show encodings for EDX.

For all feature flags, a 1 indicates that the feature is supported. Use Intel to properly interpret feature flags.

NOTE

Software must confirm that a processor feature is present using feature flags returned by CPUID prior to using the feature. Software should not depend on future offerings retaining all features.

ECX 0

RDRAND F16C AVX OSXSAVE XSAVE AES TSC-Deadline POPCNT MOVBE x2APIC

xTPR Update Control CMPXCHG16B

EDX

PBE-Pend. Brk. EN. TM-Therm. Monitor HTT-Multi-threading SS-Self Snoop SSE2-SSE2 Extensions SSE-SSE Extensions FXSR-FXSAVE/FXRSTOR MMX-MMX Technology ACPI-Thermal Monitor and Clock Ctrl DS-Debug Store CLFSH-CFLUSH instruction PSN-Processor Serial Number PSE-36 - Page Size Extension PAT-Page Attribute Table CMOV-Conditional Move/Compare Instruction MCA-Machine Check Architecture PGE-PTE Global Bit MTRR-Memory Type Range Registers SEP-SYSENTER and SYSEXIT APIC-APIC on Chip CX8-CMPXCHG8B Inst. MCE-Machine Check Exception PAE-Physical Address Extensions MSR-RDMSR and WRMSR Support TSC-Time Stamp Counter PSE-Page Size Extensions DE-Debugging Extensions VME-Virtual-8086 Mode Enhancement FPU-x87 FPU on Chip

Reserved

OM16523

INPUT EAX = 2: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX

When CPUID executes with EAX set to 2, the processor returns information about the processor’s internal TLBs, cache and prefetch hardware in the EAX, EBX, ECX, and EDX registers. The information is reported in encoded form and fall into the following categories:

• The least-significant byte in register EAX (register AL) indicates the number of times the CPUID instruction must be executed with an input value of 2 to get a complete description of the processor’s TLB/Cache/Prefetch hardware. The Intel Xeon processor 7400 series will return a 1.
• The most significant bit (bit 31) of each register indicates whether the register contains valid information (set to 0) or is reserved (set to 1).
• If a register contains valid information, the information is contained in 1 byte descriptors. There are four types of encoding values for the byte descriptor, the encoding type is noted in the second column of Table 3-22. Table 3-22 lists the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache, prefetch, or TLB types. The descriptors may appear in any order. Note also a processor may report a general descriptor type (FFH) and not report any byte descriptor of “cache type” via CPUID leaf 2. Table 3-22. Encoding of CPUID Leaf 2 Descriptors

INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level

When CPUID executes with EAX set to 04H and ECX contains an index value, the processor returns encoded data that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid index values start from 0.

Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an index value of 0, until the parameters report the value associated with the cache type field is 0. The architecturally defined fields reported by deterministic cache parameters are documented in Table 3-17.

This Cache Size in Bytes

= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)

= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)

The CPUID leaf 04H also reports data that can be used to derive the topology of processor cores in a physical package. This information is constant for all valid index values. Software can query the raw data reported by executing CPUID with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm described in Chapter 8, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

INPUT EAX = 05H: Returns MONITOR and MWAIT Features

When CPUID executes with EAX set to 05H, the processor returns information about features available to MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power management. See Table 3-17.

INPUT EAX = 06H: Returns Thermal and Power Management Features

When CPUID executes with EAX set to 06H, the processor returns information about thermal and power management features. See Table 3-17.

INPUT EAX = 07H: Returns Structured Extended Feature Enumeration Information

When CPUID executes with EAX set to 07H and ECX = 0, the processor returns information about the maximum input value for sub-leaves that contain extended feature flags. See Table 3-17.

When CPUID executes with EAX set to 07H and the input value of ECX is invalid (see leaf 07H entry in Table 3-17), the processor returns 0 in EAX/EBX/ECX/EDX. In subleaf 0, EAX returns the maximum input value of the highest leaf 7 sub-leaf, and EBX, ECX & EDX contain information of extended feature flags.

INPUT EAX = 09H: Returns Direct Cache Access Information

When CPUID executes with EAX set to 09H, the processor returns information about Direct Cache Access capabilities. See Table 3-17.

INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features

When CPUID executes with EAX set to 0AH, the processor returns information about support for architectural performance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see Table 3-17) is greater than Pn 0. See Table 3-17.

For each version of architectural performance monitoring capability, software must enumerate this leaf to discover the programming facilities and the architectural performance events available in the processor. The details are described in Chapter 23, “Introduction to Virtual-Machine Extensions,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C.

INPUT EAX = 0BH: Returns Extended Topology Information

When CPUID executes with EAX set to 0BH, the processor returns information about extended topology enumeration data. Software must detect the presence of CPUID leaf 0BH by verifying (a) the highest leaf index supported by CPUID is >= 0BH, and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-17.

INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information

When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector representation of all processor state extensions that are supported in the processor and storage size requirements of the XSAVE/XRSTOR area. See Table 3-17.

When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf index), the processor returns information about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area. See Table 3-17. Software can use the forward-extendable technique depicted below to query the valid sub-leaves and obtain size and offset information for each processor extended state save area:

For i = 2 to 62 // sub-leaf 1 is reserved IF (CPUID.(EAX=0DH, ECX=0):VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX Execute CPUID.(EAX=0DH, ECX = i) to examine size and offset for sub-leaf i; FI;

INPUT EAX = 0FH: Returns Platform Quality of Service (PQoS) Monitoring Enumeration Information

When CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information about the bit-vector representation of QoS monitoring resource types that are supported in the processor and maximum range of RMID values the processor can use to monitor of any supported resource types. Each bit, starting from bit 1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that software must use to query QoS monitoring capability available for that type. See Table 3-17.

When CPUID executes with EAX set to 0FH and ECX = n (n >= 1, and is a valid ResID), the processor returns information software can use to program IA32_PQR_ASSOC, IA32_QM_EVTSEL MSRs before reading QoS data from the IA32_QM_CTR MSR.

INPUT EAX = 10H: Returns Platform Quality of Service (PQoS) Enforcement Enumeration Information

When CPUID executes with EAX set to 10H and ECX = 0, the processor returns information about the bit-vector representation of QoS Enforcement resource types that are supported in the processor. Each bit, starting from bit 1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that software must use to query QoS enforcement capability available for that type. See Table 3-17.

When CPUID executes with EAX set to 10H and ECX = n (n >= 1, and is a valid ResID), the processor returns information about available classes of service and range of QoS mask MSRs that software can use to configure each class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.

METHODS FOR RETURNING BRANDING INFORMATION

Use the following techniques to access branding information:

These two methods are discussed in the following sections. For methods that are available in early processors, see Section: “Identification of Earlier IA-32 Processors” in Chapter 17 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.

The Processor Brand String Method

Figure 3-8 describes the algorithm used for detection of the brand string. Processor brand identification software should execute this algorithm on all Intel 64 and IA-32 processors.

This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the maximum operating frequency of the processor to the EAX, EBX, ECX, and EDX registers.

Input: EAX=0x80000000

CPUID

CPUID True ≥Function Extended Supported

EAX Return Value =Max. Extended CPUID Function Index

True

OM15194

How Brand Strings Work

To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-terminated.

Table 3-23 shows the brand string that is returned by the first processor in the Pentium 4 processor family.

Table 3-23. Processor Brand String Returned with Pentium 4 Processor

Extracting the Maximum Processor Frequency from Brand Strings

Figure 3-9 provides an algorithm which software can use to extract the maximum processor operating frequency from the processor brand string.

NOTE

When a frequency is given in a brand string, it is the maximum qualified frequency of the processor, not the frequency at which the processor is currently running.

The Processor Brand Index Method

The brand index method (introduced with Pentium^® III Xeon^® processors) provides an entry point into a brand identification table that is maintained in memory by system software and is accessible from system- and user-level code. In this table, each brand index is associate with an ASCII brand identification string that identifies the official Intel family and model number of a processor.

When CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can then use this index to locate the brand identification string for the processor in the brand identification table. The first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand index method is no longer supported. Use brand string method instead.

Table 3-24 shows brand indices that have identification strings associated with them.

Table 3-24. Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings

IA-32 Architecture Compatibility

CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the Intel486 processor.

Operation

IA32_BIOS_SIGN_ID MSR ← Update with installed microcode revision number;
CASE (EAX) OF
  EAX = 0:
     EAX ← Highest basic function input value understood by CPUID;
     EBX ← Vendor identification string;
     EDX ← Vendor identification string;
     ECX ← Vendor identification string;
  BREAK;
  EAX = 1H:
     EAX[3:0] ← Stepping ID;
     EAX[7:4] ← Model;
     EAX[11:8] ← Family;
     EAX[13:12] ← Processor type;
     EAX[15:14] ← Reserved;
     EAX[19:16] ← Extended Model;
     EAX[27:20] ← Extended Family;
     EAX[31:28] ← Reserved;
     EBX[7:0] ← Brand Index; (* Reserved if the value is zero. *)
     EBX[15:8] ← CLFLUSH Line Size;
     EBX[16:23] ← Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)
     EBX[24:31] ← Initial APIC ID;
     ECX ← Feature flags; (* See Figure 3-6. *)
     EDX ← Feature flags; (* See Figure 3-7. *)
  BREAK;
  EAX = 2H:
     EAX ← Cache and TLB information;
     EBX ← Cache and TLB information;
     ECX ← Cache and TLB information;
     EDX ← Cache and TLB information;
  BREAK;
  EAX = 3H:
     EAX ← Reserved;
     EBX ← Reserved;
     ECX ← ProcessorSerialNumber[31:0];
     (* Pentium III processors only, otherwise reserved. *)
     EDX ← ProcessorSerialNumber[63:32];
     (* Pentium III processors only, otherwise reserved. *
  BREAK
  EAX = 4H:
     EAX ← Deterministic Cache Parameters Leaf; (* See Table 3-17. *)
     EBX ← Deterministic Cache Parameters Leaf;
     ECX ← Deterministic Cache Parameters Leaf;
     EDX ← Deterministic Cache Parameters Leaf;
  BREAK;
  EAX = 5H:
     EAX ← MONITOR/MWAIT Leaf; (* See Table 3-17. *)
     EBX ← MONITOR/MWAIT Leaf;
     ECX ← MONITOR/MWAIT Leaf;
     EDX ← MONITOR/MWAIT Leaf;
  BREAK;
  EAX = 6H:
     EAX ← Thermal and Power Management Leaf; (* See Table 3-17. *)
     EBX ← Thermal and Power Management Leaf;
     ECX ← Thermal and Power Management Leaf;
     EDX ← Thermal and Power Management Leaf;
  BREAK;
  EAX = 7H:
     EAX ← Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-17. *)
     EBX ← Structured Extended Feature Flags Enumeration Leaf;
     ECX ← Structured Extended Feature Flags Enumeration Leaf;
     EDX ← Structured Extended Feature Flags Enumeration Leaf;
  BREAK;
  EAX = 8H:
     EAX ← Reserved = 0;
     EBX ← Reserved = 0;
     ECX ← Reserved = 0;
     EDX ← Reserved = 0;
  BREAK;
  EAX = 9H:
     EAX ← Direct Cache Access Information Leaf; (* See Table 3-17. *)
     EBX ← Direct Cache Access Information Leaf;
     ECX ← Direct Cache Access Information Leaf;
     EDX ← Direct Cache Access Information Leaf;
  BREAK;
  EAX = AH:
     EAX ← Architectural Performance Monitoring Leaf; (* See Table 3-17. *)
     EBX ← Architectural Performance Monitoring Leaf;
     ECX ← Architectural Performance Monitoring Leaf;
     EDX ← Architectural Performance Monitoring Leaf;
     BREAK
  EAX = BH:
     EAX ← Extended Topology Enumeration Leaf; (* See Table 3-17. *)
     EBX ← Extended Topology Enumeration Leaf;
     ECX ← Extended Topology Enumeration Leaf;
     EDX ← Extended Topology Enumeration Leaf;
  BREAK;
  EAX = CH:
     EAX ← Reserved = 0;
     EBX ← Reserved = 0;
     ECX ← Reserved = 0;
     EDX ← Reserved = 0;
  BREAK;
  EAX = DH:
     EAX ← Processor Extended State Enumeration Leaf; (* See Table 3-17. *)
     EBX ← Processor Extended State Enumeration Leaf;
     ECX ← Processor Extended State Enumeration Leaf;
     EDX ← Processor Extended State Enumeration Leaf;
  BREAK;
  EAX = EH:
     EAX ← Reserved = 0;
     EBX ← Reserved = 0;
     ECX ← Reserved = 0;
     EDX ← Reserved = 0;
  BREAK;
  EAX = FH:
     EAX ← Platform Quality of Service Monitoring Enumeration Leaf; (* See Table 3-17. *)
     EBX ← Platform Quality of Service Monitoring Enumeration Leaf;
     ECX ← Platform Quality of Service Monitoring Enumeration Leaf;
     EDX ← Platform Quality of Service Monitoring Enumeration Leaf;
  BREAK;
  EAX = 10H:
     EAX ← Platform Quality of Service Enforcement Enumeration Leaf; (* See Table 3-17. *)
     EBX ← Platform Quality of Service Enforcement Enumeration Leaf;
     ECX ← Platform Quality of Service Enforcement Enumeration Leaf;
     EDX ← Platform Quality of Service Enforcement Enumeration Leaf;
  BREAK;
BREAK;
  EAX = 80000000H:
     EAX ← Highest extended function input value understood by CPUID;
     EBX ← Reserved;
     ECX ← Reserved;
     EDX ← Reserved;
  BREAK;
  EAX = 80000001H:
     EAX ← Reserved;
     EBX ← Reserved;
     ECX ← Extended Feature Bits (* See Table 3-17.*);
     EDX ← Extended Feature Bits (* See Table 3-17. *);
  BREAK;
  EAX = 80000002H:
     EAX ← Processor Brand String;
     EBX ← Processor Brand String, continued;
     ECX ← Processor Brand String, continued;
     EDX ← Processor Brand String, continued;
  BREAK;
  EAX = 80000003H:
     EAX ← Processor Brand String, continued;
     EBX ← Processor Brand String, continued;
     ECX ← Processor Brand String, continued;
     EDX ← Processor Brand String, continued;
  BREAK;
  EAX = 80000004H:
     EAX ← Processor Brand String, continued;
     EBX ← Processor Brand String, continued;
     ECX ← Processor Brand String, continued;
     EDX ← Processor Brand String, continued;
  BREAK;
  EAX = 80000005H:
     EAX ← Reserved = 0;
     EBX ← Reserved = 0;
     ECX ← Reserved = 0;
     EDX ← Reserved = 0;
  BREAK;
  EAX = 80000006H:
     EAX ← Reserved = 0;
     EBX ← Reserved = 0;
     ECX ← Cache information;
     EDX ← Reserved = 0;
  BREAK;
  EAX = 80000007H:
     EAX ← Reserved = 0;
     EBX ← Reserved = 0;
     ECX ← Reserved = 0;
     EDX ← Reserved = Misc Feature Flags;
  BREAK;
  EAX = 80000008H:
     EAX ← Reserved = Physical Address Size Information;
     EBX ← Reserved = Virtual Address Size Information;
     ECX ← Reserved = 0;
     EDX ← Reserved = 0;
  BREAK;
  EAX >= 40000000H and EAX <= 4FFFFFFFH:
  DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)
     (* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)
     EAX ← Reserved; (* Information returned for highest basic information leaf. *)
     EBX ← Reserved; (* Information returned for highest basic information leaf. *)
     ECX ← Reserved; (* Information returned for highest basic information leaf. *)
     EDX ← Reserved; (* Information returned for highest basic information leaf. *)
  BREAK;
ESAC;

Flags Affected

None.

Exceptions (All Operating Modes)