CMPSD—Compare Scalar Double-Precision Floating-Point Values

Opcode/Instruction Op/En 64/32-bit Mode CPUID Feature Flag Description
F2 0F C2 /r ib CMPSD xmm1, xmm2/m64, imm8 RMI V/V SSE2 Compare low double-precision floating-point value in xmm2/m64 and xmm1 using imm8 as comparison predicate.
VEX.NDS.LIG.F2.0F.WIG C2 /r ib VCMPSD xmm1, xmm2, xmm3/m64, imm8 RVMI V/V AVX Compare low double precision floating-point value in xmm3/m64 and xmm2 using bits 4:0 of imm8 as comparison predicate.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
RMI ModRM:reg (r, w) ModRM:r/m (r) imm8 NA
RVMI ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8


Compares the low double-precision floating-point values in the source operand (second operand) and the destination operand (first operand) and returns the results of the comparison to the destination operand. The comparison predicate operand (third operand) specifies the type of comparison performed. The comparison result is a quadword mask of all 1s (comparison true) or all 0s (comparison false). The sign of zero is ignored for comparisons, so that -0.0 is equal to +0.0. 128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The second source operand (second operand) can be an XMM register or 64-bit memory location. The comparison predicate operand is an 8-bit immediate, bits 2:0 of the immediate define the type of comparison to be performed (see Table 3-7). Bits 7:3 of the immediate is reserved. Bits (VLMAX-1:64) of the corresponding YMM destination register remain unchanged.

The unordered relationship is true when at least one of the two source operands being compared is a NaN; the ordered relationship is true when neither source operand is a NaN.

A subsequent computational instruction that uses the mask result in the destination operand as an input operand will not generate a fault, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds to a QNaN.

Note that processors with “CPUID.1H:ECX.AVX =0” do not implement the “greater-than”, “greater-than-or-equal”, “not-greater than”, and “not-greater-than-or-equal relations” predicates. These comparisons can be made either by using the inverse relationship (that is, use the “not-less-than-or-equal” to make a “greater-than” comparison) or by using software emulation. When using software emulation, the program must swap the operands (copying registers when necessary to protect the data that will now be in the destination operand), and then perform the compare using a different predicate. The predicate to be used for these emulations is listed in Table 3-7 under the heading Emulation.

Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand CMPSD instruction, for processors with “CPUID.1H:ECX.AVX =0”. See Table 3-13. Compiler should treat reserved Imm8 values as illegal syntax.

Table 3-13. Pseudo-Ops and CMPSD

Pseudo-Op Implementation
CMPEQSD xmm1, xmm2 CMPSD xmm1,xmm2, 0
CMPLTSD xmm1, xmm2 CMPSD xmm1,xmm2, 1
CMPLESD xmm1, xmm2 CMPSD xmm1,xmm2, 2
CMPUNORDSD xmm1, xmm2 CMPSD xmm1,xmm2, 3
CMPNEQSD xmm1, xmm2 CMPSD xmm1,xmm2, 4
CMPNLTSD xmm1, xmm2 CMPSD xmm1,xmm2, 5
CMPNLESD xmm1, xmm2 CMPSD xmm1,xmm2, 6
CMPORDSD xmm1, xmm2 CMPSD xmm1,xmm2, 7

The greater-than relations not implemented in the processor require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact.)

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Enhanced Comparison Predicate for VEX-Encoded VCMPSD VEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source operand (third operand) can be an XMM register or a 64-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed. The comparison predicate operand is an 8-bit immediate:

Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates shown in Table 3-9, software emulation is no longer needed. Compilers and assemblers may implement the following three-operand pseudo-ops in addition to the four-operand VCMPSD instruction. See Table 3-14, where the notations of reg1 reg2, and reg3 represent either XMM registers or YMM registers. Compiler should treat reserved Imm8 values as illegal syntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic interface.

: Pseudo-Op VCMPEQSD reg1, reg2, reg3 VCMPLTSD reg1, reg2, reg3 VCMPLESD reg1, reg2, reg3 VCMPUNORDSD reg1, reg2, reg3 VCMPNEQSD reg1, reg2, reg3 VCMPNLTSD reg1, reg2, reg3 VCMPNLESD reg1, reg2, reg3 VCMPORDSD reg1, reg2, reg3 VCMPEQ_UQSD reg1, reg2, reg3 VCMPNGESD reg1, reg2, reg3 VCMPNGTSD reg1, reg2, reg3 VCMPFALSESD reg1, reg2, reg3 VCMPNEQ_OQSD reg1, reg2, reg3 VCMPGESD reg1, reg2, reg3 VCMPGTSD reg1, reg2, reg3 Pseudo-Op VCMPTRUESD reg1, reg2, reg3 VCMPEQ_OSSD reg1, reg2, reg3 VCMPLT_OQSD reg1, reg2, reg3 VCMPLE_OQSD reg1, reg2, reg3 VCMPUNORD_SSD reg1, reg2, reg3 VCMPNEQ_USSD reg1, reg2, reg3 VCMPNLT_UQSD reg1, reg2, reg3 VCMPNLE_UQSD reg1, reg2, reg3 VCMPORD_SSD reg1, reg2, reg3 VCMPEQ_USSD reg1, reg2, reg3 VCMPNGE_UQSD reg1, reg2, reg3 VCMPNGT_UQSD reg1, reg2, reg3 VCMPFALSE_OSSD reg1, reg2, reg3 VCMPNEQ_OSSD reg1, reg2, reg3 VCMPGE_OQSD reg1, reg2, reg3 VCMPGT_OQSD reg1, reg2, reg3 VCMPTRUE_USSD reg1, reg2, reg3 Table 3-14. Table 3-14. Pseudo-Op and VCMPSD Implementation CMPSD Implementation VCMPSD reg1, reg2, reg3, 0 VCMPSD reg1, reg2, reg3, 1 VCMPSD reg1, reg2, reg3, 2 VCMPSD reg1, reg2, reg3, 3 VCMPSD reg1, reg2, reg3, 4 VCMPSD reg1, reg2, reg3, 5 VCMPSD reg1, reg2, reg3, 6 VCMPSD reg1, reg2, reg3, 7 VCMPSD reg1, reg2, reg3, 8 VCMPSD reg1, reg2, reg3, 9 VCMPSD reg1, reg2, reg3, 0AH VCMPSD reg1, reg2, reg3, 0BH VCMPSD reg1, reg2, reg3, 0CH VCMPSD reg1, reg2, reg3, 0DH VCMPSD reg1, reg2, reg3, 0EH Pseudo-Op and VCMPSD Implementation (Contd.) CMPSD Implementation VCMPSD reg1, reg2, reg3, 0FH VCMPSD reg1, reg2, reg3, 10H VCMPSD reg1, reg2, reg3, 11H VCMPSD reg1, reg2, reg3, 12H VCMPSD reg1, reg2, reg3, 13H VCMPSD reg1, reg2, reg3, 14H VCMPSD reg1, reg2, reg3, 15H VCMPSD reg1, reg2, reg3, 16H VCMPSD reg1, reg2, reg3, 17H VCMPSD reg1, reg2, reg3, 18H VCMPSD reg1, reg2, reg3, 19H VCMPSD reg1, reg2, reg3, 1AH VCMPSD reg1, reg2, reg3, 1BH VCMPSD reg1, reg2, reg3, 1CH VCMPSD reg1, reg2, reg3, 1DH VCMPSD reg1, reg2, reg3, 1EH VCMPSD reg1, reg2, reg3, 1FH


  0: OP3 ← EQ_OQ; OP5 ← EQ_OQ;
  1: OP3 ← LT_OS; OP5 ← LT_OS;
  2: OP3 ← LE_OS; OP5 ← LE_OS;
  3: OP3 ← UNORD_Q; OP5 ← UNORD_Q;
  4: OP3 ← NEQ_UQ; OP5 ← NEQ_UQ;
  5: OP3 ← NLT_US; OP5 ← NLT_US;
  6: OP3 ← NLE_US; OP5 ← NLE_US;
  7: OP3 ← ORD_Q; OP5 ← ORD_Q;
  8: OP5 ← EQ_UQ;
  9: OP5 ← NGE_US;
  10: OP5 ← NGT_US;
  11: OP5 ← FALSE_OQ;
  12: OP5 ← NEQ_OQ;
  13: OP5 ← GE_OS;
  14: OP5 ← GT_OS;
  15: OP5 ← TRUE_UQ;
  16: OP5 ← EQ_OS;
  17: OP5 ← LT_OQ;
  18: OP5 ← LE_OQ;
  19: OP5 ← UNORD_S;
  20: OP5 ← NEQ_US;
  21: OP5 ← NLT_UQ;
  22: OP5 ← NLE_UQ;
  23: OP5 ← ORD_S;
  24: OP5 ← EQ_US;
  25: OP5 ← NGE_UQ;
  26: OP5 ← NGT_UQ;
  27: OP5 ← FALSE_OS;
  28: OP5 ← NEQ_OS;
  29: OP5 ← GE_OQ;
  30: OP5 ← GT_OQ;
  31: OP5 ← TRUE_US;
  DEFAULT: Reserved
CMPSD (128-bit Legacy SSE version)
CMP0 ← DEST[63:0] OP3 SRC[63:0];
ELSE DEST[63:0] ← 0000000000000000H; FI;
DEST[VLMAX-1:64] (Unmodified)
VCMPSD (VEX.128 encoded version)
CMP0 ← SRC1[63:0] OP5 SRC2[63:0];
ELSE DEST[63:0] ← 0000000000000000H; FI;
DEST[127:64] ← SRC1[127:64]
DEST[VLMAX-1:128] ← 0

Intel C/C++ Compiler Intrinsic Equivalents

CMPSD for equality: __m128d _mm_cmpeq_sd(__m128d a, __m128d b)
CMPSD for less-than: __m128d _mm_cmplt_sd(__m128d a, __m128d b)
CMPSD for less-than-or-equal: __m128d _mm_cmple_sd(__m128d a, __m128d b)
CMPSD for greater-than: __m128d _mm_cmpgt_sd(__m128d a, __m128d b)
CMPSD for greater-than-or-equal: __m128d _mm_cmpge_sd(__m128d a, __m128d b)
CMPSD for inequality: __m128d _mm_cmpneq_sd(__m128d a, __m128d b)
CMPSD for not-less-than: __m128d _mm_cmpnlt_sd(__m128d a, __m128d b)
CMPSD for not-greater-than: CMPSD for not-greater-than-or-equal: __m128d _mm_cmpnge_sd(__m128d a, __m128d b) __m128d _mm_cmpngt_sd(__m128d a, __m128d b)
CMPSD for ordered: __m128d _mm_cmpord_sd(__m128d a, __m128d b)
CMPSD for unordered: __m128d _mm_cmpunord_sd(__m128d a, __m128d b)
CMPSD for not-less-than-or-equal: __m128d _mm_cmpnle_sd(__m128d a, __m128d b)
VCMPSD: __m128 _mm_cmp_sd(__m128 a, __m128 b, const int imm)

SIMD Floating-Point Exceptions

Invalid if SNaN operand, Invalid if QNaN and predicate as listed in above table, Denormal.

Other Exceptions

See Exceptions Type 3.